Designer face challenges in interconnection due to large number of components. Interconnection and power consumption plays essential position on this paper. The drawbacks of previous paper tells approximately the interconnection occupies greater area and also consume more power. The Binary logic circuits layout is constrained by using the requirement of number of interconnections which increases the chip area, delay and power consumption with boom in logic. So we propose new techniques that going to be reducing interconnection of the circuit as well as power consumptions. Multiple-valued logic can lessen the desired interconnections. On this paper recommended a Quaternary to Binary decoder to reduce the control lines in multiplexer is one of the vital parts of the processing element and therefore it has a focal point of research. Therefore design of adders through multiplexer using multi valued logic can show to be very beneficial. So we introduce a full adder prototype based totally at the designed LUT. It’s capable of operate at 195MHz at the same time as power consuming 0.81mW using Xilinx14.2 and getting the simulation results through the Modelsim. The received consequences give an explanation for the perfect quaternary operation and make certain the power efficiency of the new techniques.